1. Field of the Invention
The present invention relates to a charge pump circuit suitably usable in a PLL circuit, and a PLL circuit using the charge pump circuit, and, more particularly, to glitch compensation.
2. Description of the Related Art
A PLL (Phase Locked Loop) synthesizer used in wireless devices, etc., is configured, for example, as shown in FIG. 7 where a VCO (Voltage Controlled Oscillator) 1, a reference frequency oscillator 3 and a loop filter 4 are externally attached to a PLL IC 2, and an oscillation frequency of the VCO 1 for use as a local oscillator or the like is controlled as follows.
An oscillation signal of the VCO 1 is input into the PLL IC 2, wherein a frequency of the oscillation signal is divided at a predetermined frequency-dividing ratio by a prescaler 5 and further divided by a frequency divider 6, and a resulting signal is input into a phase detector 7 as a frequency-divided signal. Meanwhile, an oscillation signal of the oscillator 3 is input into the PLL IC 2, wherein a frequency of the oscillation signal is divided by a frequency divider 8, and a resulting signal is input into the phase detector 7 as a frequency-divided signal. In cases where the phase detector 7 is configured as a tri-state type, it is operable to compare between respective phases of the frequency-divided signal from the VCO 1 and the frequency-divided signal from the oscillator 3, and output an error signal having a pulse width with the same time period as a difference between the phases, for example, as an UP signal, if the phase difference is a positive value, or as a DOWN signal, if the phase difference is a negative value.
A charge pump circuit 9 is operable, when the UP signal is input thereinto, to output (source) a given current value ICP from an output terminal thereof, just for the same time period as a pulse width of the UP signal, or, when the DOWN signal is input thereinto, to draw a given current value ICP from the output terminal thereof, just for the same time period as a pulse width of the DOWN signal, or, when both the UP and DOWN signals are in an OFF state, to place the output terminal in a high impedance state.
Current pulses output from the charge pump circuit 9 are converted into a voltage by a loop filter 4, and the voltage is applied from the loop filter 4 to the VCO 1 as a tuning voltage. In the PLL synthesizer in the example shown in FIG. 7, a phase comparison output from the phase detector 7 is controlled to become zero. In other words, a signal to be obtained by dividing a frequency of an oscillation signal of the VCO 1 by the frequency divider 6 is controlled to be synchronized and to have the same frequency with a signal obtained by dividing a frequency of an oscillation signal of the oscillator 3 by the frequency divider 8. A frequency-dividing ratio N in the frequency divider 6 is set to a desired value to allow the VCO 1 to output a stable oscillation signal having a frequency of N×fref, wherein fref is an oscillation frequency of the signal output from the frequency divider 8.
Such a PLL synthesizer requires a PLL charge pump circuit capable of outputting each of positive and negative constant currents having the same absolute value, just for the same time period as a pulse width of a respective one of the UP and DOWN signals, and in a certain output voltage range, accurately and rapidly. As an example of the PLL charge pump circuit, there has been known a circuit of a type in which each of a main-output side current path comprising series-connected two switches and having an output terminal, and an auxiliary-output side current path having the same configuration as that of the main-output side current path, is provided between current-supplying (current-sourcing) and current-drawing constant current sources, wherein one of the current path for a supply (source) current flow and the current path for a sink current flow is selected by the switches, so that an output of a positive or negative constant current is initiated or stopped at a timing designated by switching control input signals. For the sake of descriptive simplification, this type of charge pump will hereinafter be referred to as “differential switching charge pump (DSCP)”.
FIG. 8 is a circuit diagram showing one example of a typical charge pump circuit 11 of the DSCP. In the charge pump circuit 11, a diode-connected PMOS transistor q1, a constant current source ic and a diode-connected NMOS transistor q2 are connected in series between two power supply lines 13, 14 from a DC power supply 12 generating a power supply voltage vdc. A gate of the PMOS transistor q1, and a gate of the NMOS transistor q2, are connected, respectively, to a gate of a PMOS transistor q3 of the same type and size as the PMOS transistor q1, and a gate of a NMOS transistor q4 of the same type and size as the NMOS transistor q2, to form current mirror circuits. A drain of the NMOS transistor q4 is connected to a source of an NMOS transistor q6 and a source of an NMOS transistor q8. A drain of the PMOS transistor q3 is connected to a source of a PMOS transistor q5 and a source of a PMOS transistor q7. The transistor q3 corresponds to the current-supplying constant current source, and the transistor q4 corresponds to the current-drawing constant current source. A drain of each of the transistors q7, q8 is connected to an output terminal 15 of the charge pump circuit 11, to provide the main-output side current path. A drain of the transistor q6 is connected to the positive power supply lines 13, and a drain of the transistor q5 is grounded, to provide the auxiliary-output side current path.
In cases where each of the UP signal and the DOWN signal from the phase detector 7 is output based on a positive logic, the UP signal, the DOWN signal, an UPB signal which is an inverted signal of the UP signal, and a DOWNB signal which is an inverted signal of the DOWN signal, are applied to a gate of the transistor q5, a gate of the transistor q8, a gate of the transistor q7, and a gate of the transistor q6, respectively.
The charge pump circuit 11 configured as above operates as follows. Given that an output current of the constant current source ic is “ic”, a drain current of each of the transistors q3, q4 becomes equal to ic, ideally. When the UP signal is equal to “1”, the transistor q7 is placed in an ON state, and the transistor q5 is placed in an OFF state, whereas, when the UP signal is equal to “0”, the transistor q5 is placed in an ON state, and the transistor q7 is placed in an OFF state. Further, when the DOWN signal is equal to “1”, the transistor q8 is placed in an ON state, and the transistor q6 is placed in an OFF state, whereas, when the DOWN signal is equal to “0”, the transistor q6 is placed in an ON state, and the transistor q8 is placed in an OFF state.
Therefore, when the UP signal is “1” and the DOWN signal is “0”, the drain current of the transistor q3 entirely flows toward the main-output side current path, so that a constant current having the current value ic is supplied from the charge-pump output terminal 15, whereas, when the UP signal is “0” and the DOWN signal is “1”, the drain current of the transistor q4 entirely flows in from the main-output side current path, so that a constant current having the current value ic is sunk from the charge-pump output terminal 15. Further, when the UP signal is “0” and the DOWN signal is “0”, the drain current of the transistor q4 entirely flows in from the auxiliary-output side current path, and the drain current of the transistor q3 entirely flows toward the auxiliary-output side current path, so that the charge-pump output terminal 15 is placed in the high impedance state.
In the above example, the drains of the transistors q7, q8 on the main-output side current path is connected to the loop filter 4 of the PLL circuit via the output terminal 15. Thus, when the transistor q7 is placed in the ON state and the transistor q5 is placed on the OFF state, a current is supplied from the charge pump circuit 11 to the loop filter, whereas, when the transistor q8 is placed in the ON state and the transistor q6 is placed on the OFF state, the charge pump circuit 11 draws a current from the loop filter. Further, each of the current to be supplied from the charge pump circuit 11 and the current to be sunk in the charge pump circuit 11 has the constant current value ic, ideally, the same value.
As above, the PLL charge pump circuit 11 is required to output each of positive and negative current pulses each having a constant value, rapidly and accurately according to a phase difference signal (the UP signal, the DOWN signal) input thereinto. However, generally, a current pulse output from the charge pump circuit 11 involves a so-called glitch, and thereby form a distorted waveform. The reason for distortion of the current pulse waveform can be explained as follows.
Given that: each of the transistors q5 to q8 is an ideal switch, i.e., has an ON-resistance of 0Ω; and a potential at a node p1 connecting to the sources of the transistors q5, q7 and the drain of the transistor q3, a potential at a node p2 connecting to the sources of the transistors q6, q8 and the drain of the transistor q4, and a potential at a node pa connecting to the drains of the transistors q7, q8 and the output terminal 15, are v1, v2 and va, respectively. Further, given that each of the transistors q3, q4 acts as an ideal constant current source, and the drain current thereof is constant irrespective of a drain-source voltage thereof.
Firstly, a source-current switching operation under a condition that the DOWN signal is “0” will be described. When the UP signal is “0”, the transistor q7 and the transistor q5 are placed in the OFF state and the ON state, respectively, as mentioned above, and thereby the potential v1 becomes equal to a ground potential (0 V). Then, when the UP signal is changed from “0” to “1”, the transistor q7 and the transistor q5 are changed to the ON state and the OFF state, respectively, as mentioned above, and thereby the potential v1 is changed from the ground potential to the potential va.
In this case, there is a parasitic capacitance between the drain and source of the transistor q3. Given that a value of the parasitic capacitance is Cds3, a voltage Vds3=vdc−v1 is applied to the parasitic capacitance, and a charge amount Qds3=Cds3×Vds3 is charged in the parasitic capacitance. Vds3 equals vdc before change of the UP signal. Along with the change in state of the UP signal, a voltage change ΔVds3=va occurs in the parasitic capacitance. Simultaneously, the charge amount to be charged in the parasitic capacitance is reduced by ΔQds3=Cds3×va. This means that electric charges are supplied from the parasitic capacitor to the loop filter 4 in a charge amount of ΔQds3 through the transistor switch q7 and the charge-pump output terminal 15, at and after a timing when the UP signal is changed from “0” to “1”, because, generally, va>0 (V).
A charge-pump source current during a period where the charge transfer from the parasitic capacitor occurs has a value derived by adding a rate of the charge transfer to the constant current ic. This means that an ideal rectangular pulse waveform is distorted around a rising edge of a charge-pump output current pulse. Such a local error in the current pulse is called a glitch. Further, considering a sink-current switching operation under a condition that the UP signal is “0”, it turns out that, in the charge pump circuit 11, a glitch also appears in a sink current pulse.
If the glitch occurs in a charge-pump output current pulse, phase noise characteristics of a PLL oscillation output will deteriorate. Thus, it is desirable to suppress the glitch. Therefore, as means to suppress a glitch in a charge-pump output current pulse, there is a technique as disclosed, for example, in U.S. Pat. No. 5,101,117 (D1). FIG. 9 shows a charge pump circuit 21 according to this conventional technique. The charge pump circuit 21 is similar to the aforementioned charge pump circuit 11. Thus, an equivalent element or component to that of the charge pump circuit 11 is defined by a common reference numeral or code, and its description will be omitted.
In the charge pump circuit 21, the drain of the transistor q5 is connected to the drain of the transistor q6. Given that a potential of a node pb therebetween is vb. In the charge pump circuit 21, an operational amplifier 22 is added to compensate for the glitch. The operational amplifier 22 has an inverting input terminal and an output terminal each connected to the node pb, and a non-inverting input terminal connected to the node pa, wherein it operates as a voltage follower to constantly keep the potential vb at the same value as the potential va.
Thus, even if the UP signal is changed in the aforementioned manner, the drain potential v1 of the transistor q3 is not changed, before and after the transition, so that the variation amount ΔQds3 of electric charges charged in the source-drain parasitic capacitance of the transistor q3 becomes zero. In this manner, a drain current value of the transistor q3 is constantly kept at the constant current ic, and a source current pulse waveform output from the charge pump circuit 21 is formed as a rectangular waveform having a maximum current value of ic, and no glitch.
While the above description has been made about glitch compensation for the current supplying (sourcing) operation of the charge pump 21 based on the PMOS transistors q5, q7, q3, glitch compensation is also performed for the current drawing operation of the charge pump 21 based on the NMOS transistors q6, q8, q4, in the same manner.
An error current arising from a drain-source parasitic capacitance of the current-source transistors q3, q4 becomes a major factor causing a slow glitch. As used herein, the term “slow glitch” means an error current having a slow attenuation which is observed during a period where an output current value converges to a steady current value (ic) after a rising edge of an output current pulse of a charge pump circuit. However, a glitch occurring in the output current pulse of the charge pump circuit also includes an extremely fast spike-like glitch occurring just after rising or falling of an input pulse, in addition to the slow glitch. The circuit illustrated in FIG. 9 cannot compensate for this type of glitch. The present invention is also not particularly intended to compensate for it.
In the above conventional charge pump circuit, a voltage follower composed of the operational amplifier 22 is added to the DSCP to output constant current pulses reduced in glitch. However, this technique involves the following disadvantages.
(i) Generally, an operational amplifier circuit is provided with a phase compensation capacitor to suppress unstable oscillation. An adequate capacitance value of the phase compensation capacitor is about several tens of pF, and thereby a relatively large on-die area is required to form the phase compensation capacitor in an integrated circuit. This becomes a factor causing an increase in production cost of a PLL IC.
(ii) In an operational amplifier for use in a glitch compensation circuit of a DSCP, it is preferable that a maximum output current value of the operational amplifier is equal to or greater than a charge-pump output current value. Thus, particularly, in a DSCP having a relatively large output current value, it is necessary to perform glitch compensation, using an operational amplifier which comprises an output stage with a relatively large maximum output current and has a relatively large on-die occupancy area. This also becomes a factor causing an increase in production cost of a PLL IC.
(iii) Generally, an operational amplifier in a glitch compensation circuit added to a DSCP is constantly in an operating state. Thus, due to the addition of the glitch compensation circuit, an amount of energy consumption of the DSCP is increased by the power consumption of the operational amplifier×an operating time. Consequently, an amount of energy consumption of a PLL IC is also increased, causing a shortening of battery run time in mobile applications.